With the advent of the information age, personal computers (PC's) have created a profound impact on society as a whole. Together with an associated printer device, individuals may now print from PC's documents that were once typed by typewriter or type-set by hand. In such operations, the data coming from the PC is provided via a parallel interface which is located within the printer device. In some printer applications it is necessary to store an incoming word byte from a computer in a row format and allow the printer to read individual bits of each word in a column format.
Typical arrangements for implementing the requirement to write word bytes in a row format and read bits of data in a column format employ columns of shift registers coupled together in parallel. Each bit of an incoming word is stored in a corresponding location of a register column. As the next word arrives, each shift register shifts down the bits of the previous word by one location. After the time that a plurality of words, such as 32 words, each 32 bits long, have arrived, data stored in each shift register column, is read, one column at a time.
An example of the utilization of such row to column transformation may be found in Hewlett-Packard printers which write data words in row arrangements using standard RS232 bust interface, and read the data words in a column arrangement.
The use of multiple shift registers for the row to column transformation discussed above may lead to throughput delays and may also be costly. Thus, there is a need for an improved data transformation arrangement that leads to substantially fast response time and that is substantially less costly to manufacture.